A significant component of a processor design is the control logic, which dictates how data flows through the circuit. We propose a method for using program synthesis to automatically generate control logic for datapath sketches, leveraging formal specifications to extract ISA semantics. We create a parser and symbolic executor for Sail specifications that automatically constructs synthesis goals for a given ISA. Synthesizing control logic from a formal specification lets hardware developers use less effort to produce more efficient, correct-by-construction designs.

Wed 15 Jun

Displayed time zone: Pacific Time (US & Canada) change

17:30 - 19:00
Student Research Competition (SRC) Session and ReceptionSRC at Beach North
17:30
90m
Poster
Control Logic Synthesis Using Formal ISA Specifications
SRC
Benjamin Darnell University of California, Santa Barbara
Media Attached
17:30
90m
Poster
Coupled Applicative Functors
SRC
Lisa Vasilenko IMDEA Software Institute
Media Attached
17:30
90m
Poster
Program Synthesis for Processor Development Using Formal Specifications
SRC
Zachary Sisco UC Santa Barbara
Media Attached
17:30
90m
Poster
Path Alignment Automata are Probabilistic Couplings
SRC
Qian Meng Cornell university
Media Attached
17:30
90m
Poster
Multi-Phase Invariant Synthesis
SRC
Daniel Riley Florida State University
Media Attached
17:30
90m
Poster
Finding Good Generators with Multi-Armed Bandits
SRC
Joseph W. Cutler University of Pennsylvania
Media Attached
17:30
90m
Poster
Impacts of Range Reduction on Polynomial Approximation Efficiency
SRC
Sehyeok Park Rutgers University
Media Attached
17:30
90m
Poster
Automating NISQ Application Design with Meta Quantum Circuits with Constraints (MQCC)
SRC
Haowei Deng University of Maryland at College Park
Media Attached
17:30
90m
Poster
A Type System for Safe Intermittent Computing
SRC
Milijana Surbatovich Carnegie Mellon University
Media Attached
17:30
90m
Poster
PBUnit: A Live Programming Environment for Unit Testing
SRC
Justin Du University of California, San Diego, Mandeep Syal University of California, San Diego, Thanh-Nha Tran University of California, San Diego
Media Attached
17:30
90m
Poster
Visualization with Refinement Types
SRC
Junrui Liu University of California, Santa Barbara
Media Attached