While field-programmable gate arrays (FPGAs) provide an opportunity to co-design applications with hardware accelerators, they remain difficult to program. High-level synthesis (HLS) tools promise to raise the level of abstraction by compiling C or C ++ to accelerator designs. Repurposing legacy software languages, however, requires complex heuristics to automatically map unrestricted imperative code onto hardware structures. We find that the black-box heuristics in HLS tools can be unpredictable: changing parameters in the program that should improve performance can counterintuitively yield slower and larger FPGA implementations. This paper proposes a type system that restricts HLS to programs that can predictably compile to hardware accelerators. The key idea is to model consumable hardware resources with a time-sensitive affine type system that prevents conflicting simultaneous uses of the same hardware structure. We implement the type system in Dahlia, a programming language that compiles to HLS C ++ , and evaluate how its type system can reduce the size of HLS parameter spaces while accepting Pareto-optimal designs.